1. Field of the Invention
The present disclosure relates to a method for controlling programming voltage levels of non-volatile memory cells correlated to the cell features.
More particularly, but not exclusively, the present disclosure relates to a method for controlling programming voltage levels of non volatile-memory cells comprising:
providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage;
providing a reference cell crossed by a cell current.
The present disclosure also relates to a programming voltage regulator of non-volatile memory cells.
More specifically but not exclusively, the present disclosure relates to a programming voltage regulator of non-volatile memory cells of the type comprising at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with an output terminal thereof, to a resistive divider, inserted in turn between a programming voltage reference and said second voltage reference and connected to at least an output terminal of said regulator, effective to supply said programming voltage to said non-volatile memory cells.
2. Description of the Related Art
As it is well known, non-volatile memory devices, particularly EEPROM and FLASH devices, are used to store large amounts of data, for example in the digital audio and video field which is presently rapidly growing. In fact, digital audio and video applications require memory devices having increasing sizes to satisfy the need to store several musical tracks on a same medium or to increase photographic quality, for example by increasing the number of shooting pixels.
Non-volatile multilevel memories have recently come into the market, i.e., memories in which several information bits can be stored per cell. These memories seem to be particularly effective to satisfy the above needs.
Known memory devices use as elementary cell a floating gate MOS transistor and they exploit the possibility of modulating the cell threshold voltage to distinguish two logic states. A first logic state (logic “1”) corresponds to a situation in which the floating gate does not comprise any charge, typical for example of a virgin or erased cell. Another logic state (logic “0”) corresponds to the case in which the floating gate stores a number of electrons being sufficient to determine a macroscopic increase of the threshold thereof, thus determining the programmed cell state.
These devices must be thus equipped with suitable voltage regulators for generating programming voltages and storing the charge in the floating gate. It should be noted that programming voltages should be kept in a limited range of values in order to ensure a correspondence between a generic programming pulse and a corresponding threshold voltage step of programmed cells.
In multilevel memories the charge stored in the floating gate is further split, generating a number of distributions corresponding to 2nb where “nb” is the number of bits to be stored in a single cell. In this case, even more precise voltage regulators should be used, which respect the distance reduction in terms of threshold between the different distributions.
In the case of a multilevel memory, the difference reduction between the threshold voltages corresponding to the different levels of charge storable in the floating gate and, thus, between the different cell conduction levels requires therefore a “fine” and precise control of the cell programming phase and particularly of the charge stored during this phase in the floating gate terminal.
In presently marketed non-volatile memory devices, two-level or multilevel, it is known to perform the cell programming phase by applying at the control gate terminal thereof a stepped voltage which increases linearly.
In practice a series of gate programming pulses differing from each other for a constant value ΔVG is used. The gate programming voltage is thus a constant pitch stepped slope while the voltage at the drain terminal and the pulse duration depend on and are determined by the cell manufacturing process.
At the end of each programming pulse, a control phase of the obtained result is performed, to verify that the desired threshold level is reached and, consequently, to stop or continue the programming phase.
It is thus possible to program multilevel memory cells at a desired threshold voltage value, by using a predetermined number of programming pulses.
The main problem of the above-described method is the intrinsic slowness thereof. In fact, multilevel cell programming requires the application of a series of pulses to the cell control gate, starting from the lowest level, which requires more time than the single programming pulse used for two-level cells. Moreover, each level is reached only after defining the immediately lower level.
To overcome these difficulties, the Applicant itself has provided in the European patent application no. 02425293.4 filed on May 13, 2002 a programming method providing the application at drain terminals of a given memory word cells to be programmed of different voltage values according to the threshold to be reached. The different drain voltages, corresponding each to a predetermined level, are chosen so as to favor the corresponding level to be reached substantially simultaneously to the others, after an appropriate number of pulses independently from the required final level.
Obviously, same drain voltage values will be applied to obtain same-level bits.
The appropriate number of pulses should meet two requirements; it should be the lowest possible, but in the meantime it should ensure a convenient and controlled precision in reaching each level.
In particular, the programming phase should be calibrated to ensure working levels and the division thereof being advantageously technology-linked and with a compensation feature both of the supply and of the temperature conditions in order to obtain the lowest number of programming pulses with a uniform distribution of cell threshold voltage variations.
In practice, moreover, the cell threshold voltages variations of the cell programming efficiency, or more generally of the physical features of each cell after the manufacturing process, and of supply voltage values make it difficult to obtain an efficient programming phase, since little uniform answers are obtained with very heterogeneous contexts.
The control of the programming phase is much more important when operating in “fine” regulation contexts, such as multilevel applications or with trapping devices.
It is thus fundamental to succeed in controlling the variables influencing the programming phase, at least the most significant ones, to limit the natural distribution of values connected to different memory cells in an acceptable way.